Stimuli and Testbenches

Stimuli §

Verilog circuits can be tested through simulation in software using CAD Tooling. In order to determine whether the circuit functions as intended, test data will need to be provided. A stimulus file provides and updates this data so that the circuit’s response to the changes can be monitored and compared with the expected results.

initial
	begin
	a = 0;
	#100
	a = 1;
	#100
	$stop
	end

The hash symbol (#) denotes a delay. The units of time of the delay depend on the specific setup of the simulation. It is important that the $stop instruction is included at the end to terminate the simulation once the test data has all been used.

Testbenches §

A testbench is a module with no inputs or outputs. Its purpose is to be instantiated once and used to test the circuit in a simulation. It may contain stimulus data. A testbench forwards inputs from the stimulus to the Design Under Test (DUT), then allows the user to monitor the outputs.