Static RAM
Static RAM (SRAM) uses a bistable circuit comprising two transistors to hold a value. Each cell is connected to two bit lines (one is the inverse of the other) which are used to transmit the values involved in read and write operations, and a select line to signal whether to perform a read or write operation. SRAM is very fast and can be implemented with a very small circuit, but is expensive to produce in large quantities.
Dynamic RAM
Dynamic RAM (DRAM) uses a transistor to control a connection to a capacitor, which stores a single bit. The word line controls the transistor which allows the capacitor to charge from or discharge to the bit line. In order to read the value in a cell, the capacitor must discharge onto the bit line. As a result, a read operation is destructive and the read value must be immediately rewritten to the cell in order for it to persist. As well as this, the gradual leak of a capacitor’s charge over time means that each cell has to be periodically refreshed - typically more frequently than every 64ms. This constant refreshing is what leads to the name Dynamic RAM.
The use of a capacitor makes DRAM much slower than SRAM, but it is more practical and cheaper to produce in large capacities.
Synchronous and Asynchronous DRAM
Early DRAM was asynchronous. This means that it would respond to requests from the CPU as soon as it is able to. Modern DRAM is synchronous - it responds to the clock depending on the status of the control signals. Synchronous DRAM is known as SDRAM.
Double Data Rate
Unlike initial designs, modern SDRAM can have two words read each clock cycle (one on each edge of the signal). This is known as Double Data Rate, or DDR-SDRAM. There have been several generations of DDR-SDRAM, each allowing higher clock frequencies. The most modern standard (as of January 2023) is DDR5, which can handle clock speeds in excess of 5000 MHz.