Selection

Verilog has selection statements similar to those found in many programming languages.

The syntax for a case statement (equivalent of switch in most languages) is fairly typical:

case (someVar)
	0: a = x;
	1: a = y;
	2: a = z;
	default: a = x + y + z;
endcase

Note

It is important to always include a default case, even if it is known that it cannot be reached, as this prevents the synthesiser from introducing additional latches as a safety mechanism.

if statements are also free from surprises:

if (someVar == 0) a = x;
else if (someVar == 1) a = y;
else someVar = z;

Blocks are denoted in Verilog with the begin and end keywords:

if (someVar == 0)
begin
	x = 1;
	y = 2;
	z = 3;
end