Items in memory are identified by unique, -bit addresses. These are transmitted along -bit wide buses (such as the address bus). As such, we require a method to determine from an -bit wide signal which item in memory is specified, and to signal to this item that it is to be read from/written to. In order to achieve this, we use a decoder, which receives an -bit wide signal and takes one of control lines high (or low, in an active-low circuit).
Tip
This means that every decoder is of the format ”-to- decoder”, so a “2-to-8 decoder”, for example, does not make sense
Hierarchical Decoding
For all but the simplest systems, it is impractical to decode the whole address bus at once. As a result, a hierarchical approach is used, wherein multiple decoders are arranged in a tree-like structure, and a signal propagates through. In this system, the first decoder will enable the a single decoder in the next ‘level’, and this can continue until the address has been fully decoded.
There are many possible ways to break down a decoder. For example, a 6-64 bit decoder can be implemented in any of the following ways:
- two 5-to-32 bit decoders
- four 4-to-16 bit decoders
- eight 3-to-8 bit decoders
- sixteen 2-to-4 bit decoders
Two-Dimensional Decoding
Arranging memory in a single, linear array is impractical for systems with large addresses. In order to simplify the process, a two-dimensional structure can be used instead:
- Memory is arranged as an matrix.
- Each -bit address is broken into two parts, each bits wide.
- One of these parts is used to identify the row, and the other the column. This greatly simplifies the circuit required, as one -to- bit decoder can be replaced by two -to- bit decoders. As the complexity of a decoder does not scale linearly with the number of input bits, this is simpler to implement.
Note
The matrix does not have to be square. A 512MB memory, for example, can be split into a matrix.